Yield optimization for design library elements at library element level or at product level
US8799836B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 8, 2013 |
| Grant date | Aug 5, 2014 |
| Priority date | — |
| Expiry date | Jul 8, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2111/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one embodiment, at least one design library element having a design marker shape is applied to a yield checking tool having library element types, each having a yield checking deck threshold and a marker shape. The design marker shape is compared to each of the marker shapes. A determination is made as to whether the design library element satisfies the yield checking deck threshold associated with the library element type having a matching marker shape. In another embodiment, a product design formed from a design library elements each having a design marker shape is applied to the yield checking tool in a similar manner. In instances where the design library elements do not satisfy the yield checking deck threshold, then the design library element is updated by modifying the design library elements, placement of the design library elements in the product design, and/or wiring connecting the design library elements.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.