Semiconductor packages, methods of manufacturing the same, and semiconductor package structures including the same
US8802495B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 31, 2013 |
| Grant date | Aug 12, 2014 |
| Priority date | — |
| Expiry date | Jul 31, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3511
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of manufacturing a semiconductor package includes preparing a parent substrate including package board parts laterally spaced apart from each other, mounting a first chip including a through-via electrode on each of the package board parts, forming a first mold layer on the parent substrate having the first chips, planarizing the first mold layer to expose back sides of the first chips, etching the exposed back sides of the first chips to expose back sides of the through-via electrodes, forming a passivation layer on the planarized first mold layer, the etched back sides of the first chips, and the back sides of the through-via electrodes, and selectively removing the passivation layer to expose the back sides of the through-via electrodes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.