Gate electrode optimized for low voltage operation
US8802527B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 15, 2013 |
| Grant date | Aug 12, 2014 |
| Priority date | — |
| Expiry date | Mar 15, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/691
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A gate dielectric as formed includes a first interfacial dielectric layer and a high dielectric constant (high-k) dielectric layer containing a dielectric metal oxide. A polycrystalline semiconductor material layer is deposited on the high-k dielectric layer, and a second interfacial dielectric layer is formed at an interface between the polycrystalline semiconductor material layer and the high-k dielectric layer. A scavenging-metal-containing layer including a scavenging metal in an elemental form or in a metallic non-metal-element-containing compound is formed over the polycrystalline semiconductor material layer. A metallic compound such as a metallic nitride and a metallic carbide may be present above and/or over the scavenging-metal-containing layer. After formation of a gate stack by patterning, an anneal is performed, during which the oxygen in the interfacial dielectric layers diffuses into the scavenging-metal containing layer so that the thicknesses of the interfacial layers are reduced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.