Barrier layer on bump and non-wettable coating on trace
US8802556B2 · kind B2 · utility
1Cited by
6References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 20, 2013 |
| Grant date | Aug 12, 2014 |
| Priority date | — |
| Expiry date | Feb 20, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2224/83192
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Some implementations provide a semiconductor device that includes a die, an under bump metallization (UBM) structure coupled to the die, and a barrier layer. The UBM structure has a first oxide property. The barrier layer has a second oxide property that is more resistant to oxide removal from a flux material than the first oxide property of the UBM structure. The barrier layer includes a top portion, a bottom portion and a side portion. The top portion is coupled to the UBM structure, and the side portion is substantially oxidized.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.