3D semiconductor device and structure
US8803206B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 3, 2013 |
| Grant date | Aug 12, 2014 |
| Priority date | — |
| Expiry date | Apr 3, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A 3D semiconductor device, including: a first layer including first transistors; a second layer including second transistors; where the second transistors are aligned to the first transistors, and a first circuit including at least one of the first transistors, where the first circuit has a first circuit output connected to at least one of the second transistors, and where at least one of the second transistors is connected to a device output, and where the device output includes a contact port for connection to external devices, and where at least one of the second transistors is substantially larger than at least one of the first transistors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.