Trench MOS transistor and method of manufacturing the same
US8803231B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 3, 2012 |
| Grant date | Aug 12, 2014 |
| Priority date | — |
| Expiry date | Oct 12, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/518
Abstract
Trench portions (10) are formed in a well (5) in order to provide unevenness in the well (5). A gate electrode (2) is formed via an insulating film (7) on the upper surface and inside of the trench portions (10). A source region (3) is formed on one side of the gate electrode (2) in a gate length direction while a drain region (4) on another side. Both of the source region (3) and the drain region (4) are formed down to near the bottom portion of the gate electrode (2). By deeply forming the source region (3) and the drain region (4), current uniformly flows through the whole trench portions (10), and the unevenness formed in the well (5) increases the effective gate width to decrease the on-resistance of a semiconductor device 1 and to enhance the drivability thereof.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.