Embedded electronic device package structure
US8803310B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 8, 2013 |
| Grant date | Aug 12, 2014 |
| Priority date | — |
| Expiry date | Feb 8, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15153
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An embedded electronic device package structure includes a core layer, an electronic device, a first dielectric layer, a second dielectric layer and conductive vias. The core layer has cavity, a first surface and a second surface opposite to the first surface. The electronic device is disposed in the cavity. The first dielectric layer disposed on the first surface is filled in part of the cavity and covers one side of the electronic device. The second dielectric layer disposed on the second surface is filled in the cavity, covers another side of the electronic device and connects the first dielectric layer. The first and the second dielectric layers fully cover the electronic device. The conductive vias are disposed around the surrounding of the electronic device and penetrates through the first and the second dielectric layer and the core layer. The conductive vias respectively connects the first and the second dielectric layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.