Relaxation oscillator with self-biased comparator
US8803619B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 30, 2013 |
| Grant date | Aug 12, 2014 |
| Priority date | — |
| Expiry date | Mar 24, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/0231
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A relaxation oscillator for generating an output clock signal includes an RC circuit, a self-biased comparator stage, and a logic circuit. The RC circuit generates first and second comparator input signals that are provided to the self-biased comparator stage. The self-biased comparator stage includes first and second input stages and a voltage reference circuit. Each of the first and second input stages in conjunction with the voltage reference circuit forms a comparator, i.e., first and second comparators corresponding to the first and second input stages, respectively. The self-biased comparator stage generates first and second comparator output signals, based on the first and second comparator input signals. The first and second comparator output signals are provided to the logic circuit that generates the output clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.