PMOS pass gate
US8804407B1 · kind B1 · utility
0Cited by
11References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 12, 2011 |
| Grant date | Aug 12, 2014 |
| Priority date | — |
| Expiry date | Nov 15, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2217/0054
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An IC that includes a memory cell and a pass gate coupled to the memory cell, where the pass gate includes a PMOS transistor, is described. In one implementation, the PMOS transistor has a negative threshold voltage. In one implementation, the memory cell includes thick oxide transistors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.