Integrated circuit including semiconductor memory devices having stack structure
US8804453B2 · kind B2 · utility
2Cited by
1References
8Claims
0Family size
Assignee
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Key dates
| Filing date | Nov 19, 2012 |
| Grant date | Aug 12, 2014 |
| Priority date | — |
| Expiry date | Nov 19, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2272
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit includes a plurality of mode register set (MRS) setting blocks configured to generate a plurality of additive latency (AL) codes in response to an MRS signal, and a decoding unit configured to decoding the plurality of AL codes in response to a stack information signal to generate a plurality of AL setting signals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.