Power down of execution units for issued instruction accumulation when issue rate of instructions falls below threshold and at least two are independent

US8806253B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Tim Niggemeier · Laatzen, DE
• Harry Barowski · Balingen, DE
• Maarten J. Boersma · Holzgerlingen, DE
• Gunnar Spiess · Balingen, DE

Key dates

• Filing date: Aug 8, 2012
• Grant date: Aug 12, 2014
• Expiry date: Aug 8, 2032

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F9/3871
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

A method of power gating a microprocessor having an instruction scheduling unit for receiving issued instructions from an instruction decoder; an execution unit receiving and sending signals from and to the instruction scheduling unit; and a state machine. The method comprises: obtaining a number of instructions per cycle being issued to the instruction scheduling unit; determining, if the number of instruction per cycle being issued to the instruction scheduling unit is less than a threshold level, and then determining if at least two of the instructions being issued to the instruction scheduling unit are independent of each other only when the instructions per cycle is less than the threshold level; determining when at least two of the instructions being issued to the instruction scheduling unit are independent of each other; and power gating the microprocessor to gate off power to idle macros with a signal from the state machine.