System and methods for reasonable functional verification of an integrated circuit design
US8806401B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 27, 2013 |
| Grant date | Aug 12, 2014 |
| Priority date | — |
| Expiry date | Mar 27, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/33
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and methods for reasonable formal verification provides a user with coverage information that is used for verification signoff. The coverage is calculated based on formal analysis techniques and is provided to the user in terms of design-centric metrics rather than formal-centric metrics. Design-centric metrics include the likes of a number of reads from or writes to memories and a number of bit changes for counters, among many others. Accordingly, a setup for failure (SFF) function and a trigger the failure (TTF) function take place. During SFF formal analysis is applied in an attempt to reach a set of states close enough to suspected failure states. During TTF formal analysis is applied, starting from the SFF states, to search for a state violating a predetermined property. If results are inconclusive the user is provided with a design-centric coverage metric that can be used in signoff.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.