Producing a net topology pattern as a constraint upon routing of signal paths in an integrated circuit design
US8806405B2 · kind B2 · utility
22Cited by
5References
41Claims
0Family size
Assignee
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Key dates
| Filing date | Oct 31, 2012 |
| Grant date | Aug 12, 2014 |
| Priority date | — |
| Expiry date | Oct 31, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/394
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method is provided to produce a constraint information for use to implement a routing process used to generate routing signal lines in an integrated circuit design comprising: producing a net topology pattern structure that corresponds to a logical net that is associated with at least two instance item structures of at least one functional design, wherein the net topology pattern structure is associated with the at least two instance item structures and includes multiple constituent structures that indicate at least one constraint upon physical implementation of the logical net structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.