Integrated circuit pad modeling
US8806415B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 15, 2013 |
| Grant date | Aug 12, 2014 |
| Priority date | — |
| Expiry date | Feb 15, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2113/18
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of modeling an integrated circuit chip includes generating a model of a bond pad using a design tool running on a computer device. The method also includes connecting a first inductor, a first resistor, and a first set of parallel-resistor-inductor elements in series between a first node and a second node in the model. The method further includes connecting a second inductor, a second resistor, and a second set of parallel-resistor-inductor elements in series between the second node and a third node in the model. The first node corresponds to a first signal port of the bond pad. The second node corresponds to a second signal port of the bond pad.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.