Structure of stacking chips and method for manufacturing the same
US8809088B2 · kind B2 · utility
2Cited by
4References
5Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 13, 2013 |
| Grant date | Aug 19, 2014 |
| Priority date | — |
| Expiry date | Mar 13, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10F39/026
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A structure of stacking chips and a method for manufacturing the structure of stacking chips are provided. A wafer with optical chips and a glass substrate with signal processing chips are stacked with each other, and then subjected to ball mounting and die sawing to form the stacked packaging structure. The optical chips and the signal processing chips form the electrical connection on the surface of the glass substrate via the through holes thereof.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.