Self-aligned patterning for deep implantation in a semiconductor structure
US8809172B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 15, 2013 |
| Grant date | Aug 19, 2014 |
| Priority date | — |
| Expiry date | Mar 15, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10F39/803
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods of forming self-aligned patterns for performing oppositely doped deep implantations in a semiconductor substrate are disclosed. The semiconductor substrate has implantation and non-implantation regions. The methods include forming a hardmask pattern for a first implantation with a first conductivity-type dopant, depositing an etch stop layer, filling trenches between the hardmask pattern with a sacrificial filler material having a higher wet etch resistance than the hardmask, removing a top portion of the sacrificial filler material and the etch stop layer over a top surface of the hardmask pattern, removing the hardmask pattern in the implantation region by wet etching, and performing a second ion implantation with a second conductivity type dopant opposite of the first conductivity type.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.