Method for reducing topography of non-volatile memory and resulting memory cells
US8809179B2 · kind B2 · utility
7Cited by
6References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 9, 2007 |
| Grant date | Aug 19, 2014 |
| Priority date | — |
| Expiry date | Mar 29, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/40
Abstract
A method for forming a semiconductor structure includes providing a substrate; forming a gate stack of a flash memory cell, wherein a top portion of the gate stack comprises a capping layer; forming a gate having at least a portion over the capping layer; and reducing a thickness of the portion of the gate over the capping layer. The topography height difference between the flash memory cell and MOS devices on the same chip is reduced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.