Patent · US Active

Method for fabricating through substrate vias

US8809188B2 · kind B2 · utility

2Cited by

3References

15Claims

0Family size

Assignee

IMEC · BE

Inventors

Deniz Sabuncuoglu Tezcan · Neerwinden, BE
Yann Civale · Leuven, BE
Bart Swinnen · Holsbeek, BE
Eric Beyne · Heverlee, BE

Key dates

Filing date	Sep 17, 2010
Grant date	Aug 19, 2014
Priority date	—
Expiry date	Sep 17, 2030

Classification

Technology area (CPC H)Electricity
CPC primaryH01L2924/0002
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

A method of fabricating through substrate vias is disclosed. In one aspect, vias are etched from the backside of the substrate down to shallow trench isolation (STI) or the pre-metal dielectric stack (PMD). Extra contacts between metal 1 contact pads and the through-wafer vias are fabricated for realizing the contact between the through wafer vias and the back-end-of-line of the semiconductor chips.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.