Packaging of electronic circuitry
US8811030B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 30, 2011 |
| Grant date | Aug 19, 2014 |
| Priority date | — |
| Expiry date | May 22, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/19106
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A circuit package includes: electronic circuitry, electrically conductive material forming multiple leads, and multiple connections between the electronic circuitry and the multiple leads. A portion of the electrically conductive material associated with the multiple leads (e.g., low impedance leads supporting high current throughput) is removed to accommodate placement of the electronic circuitry. Each of the multiple leads can support high current. The multiple connections between the, the multiple leads provide connectivity between circuit nodes on the electronic circuitry and pads disposed on a planar surface of the electronic circuit package.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.