Charge cycling by equalizing and regulating the source, well, and bit line levels during write operations for NAND flash memory: verify to program transition
US8811075B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 9, 2012 |
| Grant date | Aug 19, 2014 |
| Priority date | — |
| Expiry date | Jan 9, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/5621
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In non-volatile memory devices, a write typically consists of an alternating set of pulse and verify operations. At the end of a pulse, the device must be biased properly for an accurate verify, after which the device is re-biased for the next pulse. The intervals between the pulse and verify phases are considered. For the interval after a pulse, but before establishing the verify conditions, the source, bit line, and, optionally, the well levels can be equalized and then regulated at a desired DC level. After a verify phase, but before applying the biasing the memory for the next pulse, the source and bit line levels can be equalized to a DC level.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.