Using a data ECC to detect address corruption
US8812935B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 2, 2012 |
| Grant date | Aug 19, 2014 |
| Priority date | — |
| Expiry date | Nov 24, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/19
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A system for detecting an address or data error in a memory system. During operation, the system stores a data block to an address by: calculating a hash of the address; using the calculated hash and data bits from the data block to compute ECC check bits; and storing the data block containing the data bits and the ECC check bits at the address. During a subsequent retrieval operation, the memory system uses the address to retrieve the data block containing the data bits and ECC check bits. Next, the system calculates a hash of the address and uses the calculated hash and the data bits to compute ECC check bits. Finally, the system compares the computed ECC check bits with the retrieved ECC check bits to determine whether an error exists in the address or data bits, or if a data corruption indicator is set.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.