Analog fault visualization system and method for circuit designs
US8813004B1 · kind B1 · utility
4Cited by
15References
20Claims
0Family size
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Key dates
| Filing date | Nov 21, 2012 |
| Grant date | Aug 19, 2014 |
| Priority date | — |
| Expiry date | Nov 21, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/367
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus and method for visualizing faults in a circuit design includes simulating faults for a circuit design in a layout and a schematic, editing the layout and schematic to include the simulated fault, and linking the layout and schematic with the fault simulation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.