Debugging using tagged flip-flops
US8813005B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 3, 2013 |
| Grant date | Aug 19, 2014 |
| Priority date | — |
| Expiry date | Sep 3, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/33
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Approaches for testing a module of a circuit design include tagging flip-flops in a netlist of the module with respective path names of the flip-flops from a hardware description language specification of the module. In simulating with the netlist, event data are captured to a first file. A process determines whether or not event data in the first file matches event data in a second file of event data. In response to a difference determined between the first file and the second file, an earliest occurrence of an event in the first file having an associated signal value of a first signal that does not match an associated signal value of a corresponding event in the second file is determined. The one of the plurality of flip-flops that output the first signal is determined, and the respective path name of the one flip-flop is output.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.