Control method for memory cell
US8817521B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 5, 2012 |
| Grant date | Aug 26, 2014 |
| Priority date | — |
| Expiry date | Sep 21, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/79
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A control method for at least one memory cell is disclosed. The memory cell includes a transistor and a resistor. The resistor is connected to the transistor in series between a first node and a second node. In a programming mode, the memory cell is programmed. When it is determined that the memory cell has been successfully programmed, impedance of the memory cell is in a first state. When it is determined that the memory cell has not been successfully programmed, a specific action is executed to reset the memory cell. The impedance of the memory cell is in a second state after the step resetting the memory cell. The impedance of the memory cell in the second state is higher than that of the memory cell in the first state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.