Complementary electrical erasable programmable read only memory
US8817546B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 24, 2012 |
| Grant date | Aug 26, 2014 |
| Priority date | — |
| Expiry date | Dec 1, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1045
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Complementary Electrical Erasable Programmable Read Only Memory (CEEPROM) is disclosed. CEEPROM cell comprises a pair of non-volatile memory elements and one access transistor. The two elements of the non-volatile memory pair are configured to be one with high electrical conductance and the other with low electrical conductance. The positive voltage VDD for digital value “1” and ground voltage VSS for digital value “0” are connected to the two input nodes of the two non-volatile elements respectively after configuration. The digital signal either VDD or VSS passed through the high conductance non-volatile memory element in the pair is directly accessed by the access transistor without applying a sense amplifier as the conventional EEPROM would require. Without sense amplifiers, the digital data in CEEPROM can be fast accessed. The power consumption and the silicon areas required for sense amplifiers can be saved as well.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.