Devices and methods for controlling memory cell pre-charge operations
US8817562B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 31, 2012 |
| Grant date | Aug 26, 2014 |
| Priority date | — |
| Expiry date | Oct 23, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1048
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory having a memory array having bit cells coupled to bit lines. The memory further includes a precharge circuit that precharges bit lines. The memory also includes a control circuit coupled to the precharge circuit that enables the precharge circuit at a beginning portion of a read cycle, keeps the precharge circuit disabled until an end of the read cycle, and keeps the precharge circuit disabled during a write cycle. A method of operating a memory, in which the memory includes an array of memory cells coupled to bit lines, includes precharging the bit lines at a beginning of a read cycle. The method also includes blocking precharging of the bit lines for a duration of a write cycle.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.