Method, apparatus, and system for energy efficiency and energy conservation including improved processor core deep power down exit latency by using register secondary uninterrupted power supply
US8819461B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 22, 2011 |
| Grant date | Aug 26, 2014 |
| Priority date | — |
| Expiry date | Aug 6, 2032 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments of the invention relate to improving exit latency from computing device processor core deep power down. Processor state data may be maintained during deep power down mode by providing a secondary uninterrupted voltage supply to always on keeper circuits that reside within critical state registers of the processor. When these registers receive a control signal indicating that the processor power state is going to be reduced from an active processor power state to a zero processor power state, they write critical state data from the critical state register latches to the keeper circuits that are supplied with the uninterrupted power. Then, when a register receives a control signal indicating that a processor power state of the processor is going to be increased back to an active processor power state, the critical state data stored in the keeper circuits is written back to the critical state register latches.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.