Patent · US Active

Method and system for fault containment

US8819485B2 · kind B2 · utility

3Cited by

5References

26Claims

0Family size

Assignee

Infineon Technologies AG · DE

Inventors

Antonio Vilela · Mering, DE
Andre Roger · Munich, DE

Key dates

Filing date	Mar 12, 2012
Grant date	Aug 26, 2014
Priority date	—
Expiry date	Oct 12, 2032

Classification

Technology area (CPC G)Physics
CPC primaryG06F11/1641
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Embodiments relate to systems and methods for error containment in a system comprising detecting an error by processing an input signal by multiple processing units, and delaying at least one output signal of a processing unit to enable, in case an error has been detected, modifying at least one output signal of the processing unit that would cause propagation of the error through the system.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.