Iterative decoder memory arrangement
US8819530B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 22, 2013 |
| Grant date | Aug 26, 2014 |
| Priority date | — |
| Expiry date | Aug 22, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/6561
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The present disclosure includes apparatus, systems and techniques relating to iterative decoder memory arrangement. A described apparatus includes R banks; Q banks; circuitry configured to store R data for a current codeword in a first R bank of the R banks and store R data for a previous codeword in a second R bank of the R banks; circuitry configured to alternate among the R banks for storing current codeword R data; circuitry configured to store Q data for the current codeword in a first Q bank of the Q banks and store Q data for the previous codeword in a second Q bank of the Q banks; and circuitry configured to alternate among the Q banks for storing current codeword Q data. The apparatus can include circuitry configured to interleave read accesses among the R banks.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.