Architectural physical synthesis
US8819608B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 22, 2008 |
| Grant date | Aug 26, 2014 |
| Priority date | — |
| Expiry date | Mar 31, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention discloses methods and apparatuses to design an integrated circuit. According to one aspect, the present invention circuit design discloses an iterative process of synthesis and placement where each iteration provides incremental changes on the design of the integrated circuit. The synthesis transform is then made with accurate timing information from the placement, and the process is incrementally iterative toward the final timing enclosure of the design. The incrementally iterative approach of the present invention provides a continuous advancement from synthesis to placement and vice versa, with the incremental improvements on synthesis made with knowledge of current instance placement, and the incremental improvements on placement made with knowledge of current circuit logic.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.