Dual lead frame semiconductor package and method of manufacture
US8822273B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 9, 2011 |
| Grant date | Sep 2, 2014 |
| Priority date | — |
| Expiry date | Sep 23, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package and a method for making the same are provided. In the method, a clip is used to conduct a lead frame and at least one chip. The clip has at least one second connection segment, at least one third connection segment, and at least one intermediate connection segment. The second connection segment is electrically connected to a second conduction region of the chip and a second pin of the lead frame respectively, and the third connection segment is electrically connected to a third conduction region of the chip and a third pin of the lead frame respectively. The intermediate connection segment connects the at least one second connection segment and the at least one third connection segment, and is removed in a subsequent process. Thereby, the present invention does not need to use any gold wire, which effectively saves the material cost and the processing time.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.