FinFETs and methods for forming the same
US8822290B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 25, 2013 |
| Grant date | Sep 2, 2014 |
| Priority date | — |
| Expiry date | Jan 25, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/62
Abstract
A method includes recessing isolation regions, wherein a portion of a semiconductor strip between the isolation regions is over top surfaces of the recessed isolation regions, and forms a semiconductor fin. A dummy gate is formed to cover a middle portion of the semiconductor fin. An Inter-Layer Dielectric (ILD) is formed to cover end portions of the semiconductor fin. The dummy gate is then removed to form a first recess, wherein the middle portion is exposed to the first recess. The middle portion of the semiconductor fin is removed to form a second recess. An epitaxy is performed to grow a semiconductor material in the second recess, wherein the semiconductor material is between the end portions. A gate dielectric and a gate electrode are formed in the first recess. The gate dielectric and the gate electrode are over the semiconductor material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.