Data output circuit
US8823433B2 · kind B2 · utility
4Cited by
12References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 18, 2013 |
| Grant date | Sep 2, 2014 |
| Priority date | — |
| Expiry date | Mar 18, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/1565
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A data output circuit according to one embodiment of the present invention includes: a delay control block configured to generate a clock delay signal in response to a power-up signal and a reset signal; a first delay block configured to correct a duty ratio of a rising clock according to the clock delay signal and output the corrected rising clock; and a second delay block configured to correct a duty ratio of a falling clock according to the clock delay signal and output the corrected falling clock.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.