Manufacturing method of anti punch-through leakage current metal-oxide-semiconductor transistor
US8828827B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 26, 2013 |
| Grant date | Sep 9, 2014 |
| Priority date | — |
| Expiry date | Aug 26, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/516
Abstract
A manufacturing method of an anti punch-through leakage current MOS transistor is provided. A high voltage deep first type well region and a first type light doping region are formed in a second type substrate. A mask with a dopant implanting opening is formed on the second type substrate. An anti punch-through leakage current structure is formed by implanting the first type dopant through the dopant implanting opening. A doping concentration of the first type dopant of the high voltage deep first type well region is less than that of the anti punch-through leakage current structure and greater than that of the high voltage deep first type well region. A second type body is formed by implanting a second type dopant through the dopant implanting opening. A gate structure is formed on the second type substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.