Hybrid thin film transistor, manufacturing method thereof and display panel having the same
US8829511B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 15, 2011 |
| Grant date | Sep 9, 2014 |
| Priority date | — |
| Expiry date | Dec 3, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/471
Abstract
A hybrid thin film transistor includes a first thin film transistor and a second thin film transistor. The first thin film transistor includes a first gate, a first source, a first drain and a first semiconductor layer disposed between the first gate, the first source and the first drain, and the first semiconductor layer includes a crystallized silicon layer. The second thin film transistor includes a second gate, a second source, a second drain and a second semiconductor layer disposed between the second gate, the second source and the second drain, and the second semiconductor layer includes a metal oxide semiconductor layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.