Patent · US Active

Semiconductor layer structure comprising a cavity layer and method for fabricating the semiconductor layer structure

US8829532B2 · kind B2 · utility

2Cited by

4References

33Claims

0Family size

Assignee

Siltronic AG · DE

Inventors

Brian Murphy · Pfarrkirchen, DE
Maik Häberlen · Augsburg, DE
Jörg Lindner · Bobingen, DE
Bernd Stritzker · Kissing, DE

Key dates

Filing date	Feb 2, 2007
Grant date	Sep 9, 2014
Priority date	—
Expiry date	Jan 4, 2030

Classification

Technology area (CPC H)Electricity
CPC primaryH01L21/02551
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

Semiconductor layer structure and a method for producing a structure are provided, including a substrate made of semiconductor material, on which a layer made of a second semiconductor material is situated, furthermore a region (3) enriched with impurity atoms, which region is situated either in layer (2) or at a specific depth below the interface between layer (2) and substrate (1), additionally a layer (4) within the region (3) enriched with impurity atoms, which layer comprises cavities produced by ion implantation, furthermore at least one epitaxial layer (6) applied to layer (2) and also a defect region (5) comprising dislocations and stacking faults within the layer (4) comprising cavities, the at least one epitaxial layer (6) being largely crack-free, and a residual strain of the at least one epitaxial layer (6) being less than or equal to 1 GPa.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.