Metal alloy with an abrupt interface to III-V semiconductor
US8829567B2 · kind B2 · utility
6Cited by
8References
19Claims
0Family size
Assignee
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Key dates
| Filing date | Dec 28, 2012 |
| Grant date | Sep 9, 2014 |
| Priority date | — |
| Expiry date | Jan 3, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/691
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Semiconductor structures having a first layer including an n-type III-V semiconductor material and a second layer including an M(InP)(InGaAs) alloy, wherein M is selected from Ni, Pt, Pd, Co, Ti, Zr, Y, Mo, Ru, Ir, Sb, In, Dy, Tb, Er, Yb, and Te, and combinations thereof, are disclosed. The semiconductor structures have a substantially planar interface between the first and second layers. Methods of fabricating semiconductor structures, and methods of reducing interface roughness and/or sheet resistance of a contact are also disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.