Structure and layout of a FET prime cell
US8829572B2 · kind B2 · utility
2Cited by
13References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 16, 2012 |
| Grant date | Sep 9, 2014 |
| Priority date | — |
| Expiry date | Feb 26, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/257
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Method of making a semiconductor device that includes forming a source and a drain in a substrate, forming a gate on the substrate between the source and drain, forming a substrate contact in electrical contact with the source, and forming an electrical contact to the source, drain and gate, and the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.