Resistive memory devices
US8829581B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 19, 2013 |
| Grant date | Sep 9, 2014 |
| Priority date | — |
| Expiry date | Apr 19, 2033 |
Classification
- Technology area (CPC B)Performing Operations; Transporting
- CPC primaryB82Y40/00
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
A resistive memory device includes a stack comprising conductor layers and insulator layers, with the edges of the conductor layers and insulating layers exposed on the sides of the stack. An insulator is disposed on a first side of the stack to cover exposed edges of the conductor layers on the first side of the stack. A memory layer disposed over the stack and insulator, such that the memory layer is in electrical contact with edges of the conductor layers on a second side of the stack but is insulated from edges on the first side of the stack by the insulator. A conductive ribbon is disposed over the memory layer to form programmable memory elements where the conductive ribbon crosses edges of the conductor layers on the second side of the stack.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.