Programmable clock divider
US8829953B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 9, 2014 |
| Grant date | Sep 9, 2014 |
| Priority date | — |
| Expiry date | Jan 9, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K23/667
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A programmable clock divider includes first and second comparators for generating first and second signals respectively based on a count value of a counter and a frequency ratio value. First and second flip-flops delay the first and second signals by one clock cycle of the input clock signal. An active-low latch delays the second signal by half a clock cycle of the input clock signal. A multiplexer receives the delayed first and second signals at first and second input terminals respectively and the input clock signal at a select terminal, and generates a divided clock signal. The multiplexer outputs the second delayed signal when the input clock signal is at a logic high state and outputs the first delayed signal when the input clock signal is at a logic low state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.