Semiconductor memory device including vertical channel transistors
US8830715B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 28, 2011 |
| Grant date | Sep 9, 2014 |
| Priority date | — |
| Expiry date | Jan 3, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/50
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device is disclosed. The semiconductor memory device includes a memory array block, a first word line and a second word line. The memory array block includes a plurality of adjacent columns of memory cells, each column of memory cells including a plurality of consecutive memory cells having a plurality of respective consecutive cell transistors that comprise at least a first group of cell transistors and a second group of cell transistors. The first word line is disposed above the plurality of respective consecutive cell transistors and electrically connected to the first group of cell transistors, and the second word line is disposed below the plurality of respective consecutive cell transistors and electrically connected to the second group of cell transistors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.