System and method of performing power on reset for memory array circuits
US8830780B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 15, 2013 |
| Grant date | Sep 9, 2014 |
| Priority date | — |
| Expiry date | Jan 15, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The disclosure relates to an apparatus for deactivating one or more predecoded address lines of a memory circuit in response to one or more of the predecoded address lines being activated upon powering on of at least a portion of the apparatus. In particular, the apparatus includes a memory device; an address predecoder configured to activate one or more of a plurality of predecoded address lines based on an input address, wherein the plurality of predecoded address lines are coupled to the memory device for accessing one or more memory cells associated with the one or more activated predecoded address lines; and a power-on-reset circuit configured to deactivate one or more of the predecoded address lines in response to the one or more of the predecoded address lines being activated upon powering on the at least portion of the apparatus.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.