Improving read stability of a semiconductor memory
US8830783B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 3, 2011 |
| Grant date | Sep 9, 2014 |
| Priority date | — |
| Expiry date | Apr 30, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/419
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory storage device is disclosed. The memory comprises a plurality of storage cells for storing data each storage cell comprising an access control device for providing the storage cell with access to or isolation from a data access port in response to an access control signal, access control circuitry for transmitting the access control signal along an access control line to control a plurality of the access control devices connected to the access control line. The access control circuitry responds to a data access request signal by increasing a voltage level supplied to the access control line to a first voltage level at a first average rate and then in response to receipt of a further signal increasing the voltage level supplied to the access control line to the predetermined higher voltage level, in such a way that a further average rate of increase of the voltage level from the first to the predetermined higher voltage level is lower than the first average rate of increase to the first level.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.