Detecting data transmission errors in an inter-integrated circuit (‘I2C’) system
US8832538B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 22, 2012 |
| Grant date | Sep 9, 2014 |
| Priority date | — |
| Expiry date | Dec 27, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2001/0094
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Detecting data transmission errors in an I2C system that includes a source device, an destination device, and a signal line coupling the I2C source and destination device, including: receiving, by the I2C destination device from the I2C source device, a data transmission signal, the data transmission signal encoded with a set of bits; detecting, by the I2C destination device, rise time of a preselected bit in the set of bits; if the detected rise time is less than a predefined threshold, determining that the I2C source device injected a parity bit in the signal, and if the detected rise time is not less than the predefined threshold, determining that the I2C source device did not inject a parity bit in the signal; and determining whether the data transmission signal includes an error in dependence upon the parity of the set of bits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.