Chip card contact array arrangement
US8833668B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 12, 2012 |
| Grant date | Sep 16, 2014 |
| Priority date | — |
| Expiry date | Mar 13, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06K19/07783
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In various embodiments, a chip card contact array arrangement is provided, having a carrier, a plurality of contact arrays which are arranged on a first side of the carrier, an electrically conductive structure which is arranged on a second side of the carrier, which is arranged opposite the first side of the carrier, a first plated-through hole and a second plated-through hole, wherein the first plated-through hole is coupled to the electrically conductive structure, a connecting structure which is arranged on the first side of the carrier, wherein the connecting structure connects the first plated-through hole to the second plated-through hole, the connecting structure having a longitudinal extent which runs parallel to a direction in which a contact-connection device on a reading device is moved relative to the plurality of contacts.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.