Method for fabricating a circuit
US8835101B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 7, 2011 |
| Grant date | Sep 16, 2014 |
| Priority date | — |
| Expiry date | Jun 7, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/033
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for fabricating a circuit, by defining a first set of resist features on a substrate and corresponding to a first mask layout, followed by defining a second set of resist features on the substrate corresponding to a second mask layout, wherein the second set adds to the first set for rectifying an error in either mask layout. In another aspect, the method is by defining a first set of resist features on a substrate and corresponding to a first mask layout that has an error, etching the substrate while the first set protects selected regions, defining a second set of resist features on the substrate and corresponding to a second mask layout, followed by etching the substrate to selectively remove portions of the selected regions for rectifying the error.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.