Semiconductor structure and method
US8835242B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 12, 2014 |
| Grant date | Sep 16, 2014 |
| Priority date | — |
| Expiry date | Feb 12, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D88/101
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An embodiment is a semiconductor structure. The semiconductor structure comprises at least two gate structures on a substrate. The gate structures define a recess between the gate structures, and the recess is defined by a depth in a vertical direction. The depth is from a top surface of at least one of the gate structures to below a top surface of the substrate, and the depth extends in an isolation region in the substrate. The semiconductor structure further comprises a filler material in the recess. The filler material has a first thickness in the vertical direction. The semiconductor structure also comprises an inter-layer dielectric layer in the recess and over the filler material. The inter-layer dielectric layer has a second thickness in the vertical direction below the top surface of the at least one of the gate structures. The first thickness is greater than the second thickness.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.