Transistor with primary and semiconductor spacer, method for manufacturing transistor, and semiconductor chip comprising the transistor
US8835316B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 9, 2011 |
| Grant date | Sep 16, 2014 |
| Priority date | — |
| Expiry date | Jul 20, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/258
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The disclosure provides a transistor, a method for manufacturing the transistor, and a semiconductor chip comprising the transistor. The transistor comprises: an active area, a gate stack, a primary spacer, and source/drain regions, wherein the active area is on a semiconductor substrate; the gate stack, the primary spacer, and the source/drain regions are on the active area; the primary spacer surrounds the gate stack; the source/drain regions are embedded in the active area and self-aligned with opposite sides of the primary spacer. Wherein the transistor further comprises: a silicide spacer, wherein the silicide spacer is located at opposite sides of the primary spacer, and a dielectric material is filled between the two ends of the silicide spacer in the width direction of the gate stack, so as to isolate the source/drain regions from each other.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.