Recessed gate-type silicon carbide field effect transistor and method of producing same

US8835933B2 · kind B2 · utility

Assignee

• National Institute of Advanced Industrial Science and Technology · JP

Inventors

• Takahiro Nagano · Yokohama, JP
• Mitsuo Okamoto · Tsukuba, JP
• Tsutomu Yatsuo · Hitachi, JP
• Kenji Fukuda · Ube, JP

Key dates

• Filing date: Aug 27, 2010
• Grant date: Sep 16, 2014
• Expiry date: Nov 11, 2030

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D62/8325

Abstract

A SiC MISFET, in which a source region and a drain region (3, 4) are formed in a one-conductivity-type SiC semiconductor region (2), in which a recess (5) with a predetermined depth is formed in a portion of the SiC semiconductor region sandwiched between the source and drain regions, with the recess having two side faces in contact with the source and drain regions, and a bottom face connecting the two side faces, and in which portions (3a, 4a) of the source and drain regions adjacent to the vicinity of both ends of the bottom face of the recess are thinner than other portions.