Vertical nonvolatile memory devices having reference features
US8836020B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 31, 2011 |
| Grant date | Sep 16, 2014 |
| Priority date | — |
| Expiry date | Apr 13, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/50
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device includes a substrate having a cell array region defined therein. A dummy structure is disposed on or in the substrate near a boundary of the cell array region. The memory device also includes a vertical channel region disposed on the substrate in the cell array region. The memory device further includes a plurality of vertically stacked conductive gate lines with insulating layers interposed therebetween, the conductive gate lines and interposed insulating layers disposed laterally adjacent the vertical channel region and extending across the dummy structure, at least an uppermost one of the conductive gate lines and insulating layers having a surface variation at the crossing of the dummy structure configured to serve as a reference feature. The dummy structure may include a trench, and the surface variation may include an indentation overlying the trench.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.